3rd P4 Workshop in Europe (EuroP4)

Dec 01, 2020 to Dec 01, 2020 | Virtual (Barcelona)

A presentation by the P4 Language Consortium and ONF in conjunction with CoNEXT 2020

EuroP4 2020 is the third P4 Language Consortium event in Europe. It aims to bring together P4 and P4->NetFPGA researchers from Europe and from around the world, and to foster the growth of the P4 Community.

Program

9:15 - 9:30, GMTWelcome and Introductions
Fernando Ramos and Gábor Rétvári

9:30 - 10:30, GMTKeynote talk by Laurent Vanbever (ETH Zürich)
Session Chair: Sándor Laki, Eötvös Loránd University
Title: Programmable, Hardware-Based Routing and Scheduling
Abstract: Routing and scheduling are two of the most fundamental tasks performed by any network. Routing determines the set of paths alongside which network traffic flows, while scheduling controls how traffic flows alongside these paths.
Today, these two tasks strike different trade-offs in terms of flexibility and speed. As it runs in the control plane, in software, routing tends to be flexible… but slow. In contrast, as it runs in the data plane, most of the time in hardware, scheduling tends to be inflexible… but fast.
In this talk, I will argue that this trade-off is not fundamental thanks to the recent advent of programmable data planes. More specifically, I will first argue about offloading (some) routing tasks to the hardware, so as to make them much faster. I will then argue about making packet scheduling programmable, so as to make it much more flexible. I will illustrate each proposal with examples of our recent works including Hardware-Accelerated Control Planes [HotNets’18], Blink [NSDI’19], and SP-PIFO [NSDI’20].

10:30 - 11:00, GMTVirtual coffee break

11:00 - 12:30, GMTSession 1: Use Cases
Session Chair: Noa Zilberman, University of Oxford
- 11:00 - 11:15, GMT
  Comparative Evaluation of IP-Address Anti-Spoofing Mechanisms using a P4/NetFPGA-based Switch. Harsh Gondaliya (SRM Institute of Science and Technology), Ganesh C. Sankaran (University of California, Davis), Krishna Sivalingam (Indian Institute of Technology Madras)
- 11:15 - 11:30, GMT
  Falcon - Low Latency, Network-Accelerated Scheduling. Ibrahim Kettaneh (University of Waterloo), Sreeharsha Udayashankar (University of Waterloo), Ashraf Abdel-hadi (University of Waterloo), Samer Al-Kiswany (University of Waterloo)
- 11:30 - 11:45, GMT
  SYN Flood Defense in Programmable Data Planes. Dominik Scholz (Technical University of Munich), Sebastian Gallenmüller (Technical University of Munich), Henning Stubbe (Technical University of Munich), Georg Carle (Technical University of Munich)
- 11:45 - 12:00, GMT
  P4-Protect: 1+1 Path Protection for P4. Steffen Lindner (University of Tuebingen), Daniel Merling (University of Tuebingen), Marco Häberle (University of Tuebingen), Michael Menth (University of Tuebingen)
- 12:00 - 12:30, GMT
  Panel discussion

12:30 - 13:30, GMTLunch break

13:30 - 14:30, GMTSession 2: Posters and Demos
Session Chair: Gianni Antichi, Queen Mary University of London
- Posters
  - 13:30 - 13:40, GMT
    Unleashing the performance of virtual BNG by offloading data plane to a programmable ASIC. Tomasz Osiński (Orange Labs & Warsaw University of Technology), Mateusz Kossakowski (Orange Labs), Mateusz Pawlik (Orange Labs), Jan Palimąka (Orange Labs), Michał Sala (Orange Labs), Halina Tarasiuk (Warsaw University of Technology)
  - 13:40 - 13:50, GMT
    Towards a Hybrid Next Generation NodeB. Péter Vörös (Eötvös Loránd University), Gergely Pongrácz (Ericsson Research), Sándor Laki (Eötvös Loránd University)
  - 13:50 - 14:00, GMT
    A perspective on P4-based data and control plane modularity for network automation. Eder Ollora Zaballa (Technical University of Denmark), David Franco (University of the Basque Country), Michael Stübert Berger (Denmark Techinical University), Mariavi Higuero (University of the Basque Country)
- Demos
  - 14:00 - 14:10, GMT
    A P4 Data Plane for the Quantum Internet. Wojciech Kozlowski (QuTech, Delft University of Technology), Fernando Kuipers (Delft University of Technology), Stephanie Wehner (QuTech, Delft University of Technology)
  - 14:10 - 14:20, GMT
    Developing EFSM-based stateful applications with FlowBlaze.p4 and ONOS. Daniele Moro (Politecnico di Milano), Davide Sanvito (NEC Laboratories Europe), Antonio Capone (Politecnico di Milano)
  - 14:20 - 14:30, GMT
    Pushing Network Programmability to the Limits with SRv6 uSID and P4. Ahmed Abdelsalam (Cisco Systems), Angelo Tulumello (University of Rome Tor Vergata), Marco Bonola (CNIT – National Inter University Consortium for Telecommunications), Stefano Salsano (University of Rome Tor Vergata), Clarence Filsfils (Cisco Systems)

14:30 - 15:00, GMTCoffee break

15:00 - 16:15, GMTSession 3: Architectures and Platforms
Session Chair: Robert Soulé, Yale University
- 15:00 - 15:15, GMT
  Compiling Packet Programs to Reconfigurable Switches: Theory and Algorithms. Balázs Vass (Budapest University of Technology and Economics), Erika Bérczi-Kovács (Eötvös Loránd Science University), Costin Raiciu (University Politehnica of Bucharest), Gábor Rétvári (Budapest University of Technology and Economics)
- 15:15 - 15:30, GMT
  Leveraging Target-specific Features Through P4. Alex Seibulescu (Pensando Systems, Inc.), Mario Baldi (Pensando Systems, Inc.)
- 15:30 - 15:45, GMT
  MTPSA: Multi-Tenant Programmable Switches. Radostin Stoyanov (University of Cambridge), Noa Zilberman (University of Oxford)
- 15:45 - 16:15, GMT
  Panel discussion

16:15 - 16:30, GMTClosing words
16:30 - 17:30, GMTVirtual social event

Important Dates

Abstract registration: Tuesday September 1st, 2020 (11:59PM AoE)
Abstract registration and Paper submission deadline: Tuesday, September 8th, 2020 (11:59PM AoE)
Acceptance notification: Monday, October 5th, 2020
Posters and demos deadline: Tuesday, September 8th, 2020 (11:59PM AoE)
Posters and demos notification: Monday, October 5th, 2020.
Camera ready: Thursday, October 29th, 2020 (11:59PM AoE)
Video upload: Wednesday, November 18th, 2020 (11:59PM AoE)

Participation

As a consequence of the current situation of the COVID-19 pandemic and similar to CoNEXT’20, EuroP4’20 will be a fully virtual (online) event. Please follow the updates on the CoNEXT’20 and our website for the details.

Registration

Registration is through CoNEXT 2020

General Chairs

Noa Zilberman, University of Cambridge
Robert Soulé, Yale University

Program Chairs

Fernando Ramos, University of Lisbon
Gábor Rétvári, Budapest University of Technology and Economics

Organizing Committee

Salvatore Signorello, University of Lisbon
Tamás Lévai, Budapest University of Technology and Economics

Technical Program Committee

Aurojit Panda, New York University
Ben Pfaff, VMware
Brian O’Connor, Open Networking Foundation
Christian Rothenberg, University of Campinas
Gianni Antichi, Queen Mary University of London
Gordon Brebner, Xilinx Labs
Jon Crowcroft, University of Cambridge
Marco Chiesa, KTH Royal Institute of Technology
Mario Baldi, Pensando Systems & Politecnico di Torino
Mina Tahmasbi Arashloo, Cornell University
Nate Foster, Cornell University
Paolo Costa, Microsoft Research
Roberto Bifulco, NEC Labs Europe
Sandor Laki, Eötvös Loránd University
Shir Landau Feibish, Princeton University
Theo Jepsen, Stanford University