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P4 Integrated Network Stack (PINS) is an industry collaboration bringing SDN capabilities and P4 programmability to traditional routing devices that rely on embedded control protocols (like BGP). Specifically, this project uses P4 to model the SAI pipeline, adds externally programmable extensions to the pipeline and introduces P4Runtime as a new control plane interface for controlling the pipeline.

PINS Update

Presented at P4 2022 Workshop

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Presented by Bhagat Janarthanan, Varnsi Punati, Brian O’Connor, Reshma Sundarshan

Until now, there have been two primary ways of approaching networking:
the traditional embedded routing approach (e.g. BGP) or the SDN approach
that simplifies the dataplane and centralizes the control plane off box.

 

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PINS: SDN extensibility added to traditional networks

 

 

PINS creates a hybrid model, bringing SDN programmability to traditional networking.  By adding an optional externally programmable stage to the forwarding pipeline of each switching device, networks can be built in traditional ways and augmented with advanced functionality with the aid of an external SDN controller.

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PINS Highlights

  • Hybrid Control Plane Support: Gives network operators a choice on network control plane and which parts run where (locally or remotely).
  • Opt-In Path Towards SDN: The P4Runtime server is added to SONiC as an optional interface enabling users to implement new functionality using SDN, and to incrementally migrate towards an SDN solution.
  • Familiar Interface: P4 is used to model the SAI pipeline, and enables users to control all essential networking features, including L2 bridging, L3 routing, ACLs, tunnels, and more.
  • Rapid Innovation: New features can quickly be modeled in P4 and exposed to control plane applications using P4Runtime. 
  • Automated Validation: P4Runtime enables tools to be used to test and validate every packet path automatically in the forwarding pipeline.

PINS – P4 Integrated Network Stack

Bhagat Janarthanan, Google
Brian O’connor, ONF
Reshma Sudarshan, Intel

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PINS Architectural Diagram

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PINS Community

PINS Resources

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