3rd P4 Workshop in Europe (EuroP4)

Dec 01, 2020 to Dec 01, 2020 | Barcelona, Spain

A presentation by the P4 Language Consortium and ONF in conjunction with CoNEXT 2020

EuroP4 2020 is the third P4 Language Consortium event in Europe. It aims to bring together P4 and P4->NetFPGA researchers from Europe and from around the world, and to foster the growth of the P4 Community.

EuroP4 Registration Grants

We are pleased to offer a limited number of awards supporting registration expenses associated with participating at CoNEXT 2020 and EuroP4 2020. Attendees from traditionally under-represented groups, students and recent graduates, early-career researchers in industry and non-affiliated, are particularly encouraged to apply. Should we receive more applications than the funding can support, priority will be given to applicants not otherwise able to attend the conference, and/or from regions where financial resources may not be available to cover even the lower remote registration cost.

The intent of the registration grant is to encourage a broader diversity of participation, and, as a result, award selection will prioritize applicants who are not authors. Though, everyone is encouraged to apply.

Registration grants are funded by the generous support of our sponsor APS Networks.

Award applications must be completed at the CoNEXT 2020 site. Applications will be reviewed and awards will be offered starting from November 10th, 2020. However, we will keep accepting applications even after November 10th and award grants based on availability. The applicants need to provide a resume and a short statement indicating how they would benefit from attending EuroP4 2020.

Each grant is for a nominal amount for registration for the virtual event. Details on payment/reimbursement will be announced soon.

If you have any questions about the application process, please email the TPC Co-Chairs.


  • 9:15 – 9:30, GMT

    Welcome and Introductions
    Fernando Ramos and Gabor Retvari

  • 10:30 – 11:00, GMT

    Virtual coffee break

  • 11:00 – 12:30, GMT

    Session 1: Use Cases

    • 11:00 – 11:15, GMT
      Comparative Evaluation of IP-Address Anti-Spoofing Mechanisms using a P4/NetFPGA-based Switch. Harsh Gondaliya (SRM Institute of Science and Technology), Ganesh C. Sankaran (University of California, Davis), Krishna Sivalingam (Indian Institute of Technology Madras)
    • 11:15 – 11:30, GMT
      Falcon – Low Latency, Network-Accelerated Scheduling. Ibrahim Kettaneh (University of Waterloo), Sreeharsha Udayashankar (University of Waterloo), Ashraf Abdel-hadi (University of Waterloo), Samer Al-Kiswany (University of Waterloo)
    • 11:30 – 11:45, GMT
      SYN Flood Defense in Programmable Data Planes. Dominik Scholz (Technical University of Munich), Sebastian Gallenmüller (Technical University of Munich), Henning Stubbe (Technical University of Munich), Georg Carle (Technical University of Munich)
    • 11:45 – 12:00, GMT
      P4-Protect: 1+1 Path Protection for P4. Steffen Lindner (University of Tuebingen), Daniel Merling (University of Tuebingen), Marco Häberle (University of Tuebingen), Michael Menth (University of Tuebingen)
    • 12:00 – 12:30, GMT
      Panel discussion

  • 12:30 – 13:30, GMT

    Lunch break

  • 13:30 – 15:00, GMT

    Session 2: Posters and Demos

    • Posters
      • 13:30 – 13:40, GMT
        Unleashing the performance of virtual BNG by offloading data plane to a programmable ASIC. Tomasz Osiński (Orange Labs & Warsaw University of Technology), Mateusz Kossakowski (Orange Labs), Mateusz Pawlik (Orange Labs), Jan Palimąka (Orange Labs), Michał Sala (Orange Labs), Halina Tarasiuk (Warsaw University of Technology)
      • 13:40 – 13:50, GMT
        Towards a Hybrid Next Generation NodeB. Péter Vörös (Eötvös Loránd University), Gergely Pongrácz (Ericsson Research), Sándor Laki (Eötvös Loránd University)
      • 13:50 – 14:00, GMT
        A perspective on P4-based data and control plane modularity for network automation. Eder Ollora Zaballa (Technical University of Denmark), David Franco (University of the Basque Country), Michael Stübert Berger (Denmark Techinical University), Mariavi Higuero (University of the Basque Country)
    • Demos
      • 14:00 – 14:10, GMT
        A P4 Data Plane for the Quantum Internet. Wojciech Kozlowski (QuTech, Delft University of Technology), Fernando Kuipers (Delft University of Technology), Stephanie Wehner (QuTech, Delft University of Technology)
      • 14:10 – 14:20, GMT
        Developing EFSM-based stateful applications with FlowBlaze.p4 and ONOS. Daniele Moro (Politecnico di Milano), Davide Sanvito (NEC Laboratories Europe), Antonio Capone (Politecnico di Milano)
      • 14:20 – 14:30, GMT
        Pushing Network Programmability to the Limits with SRv6 uSID and P4. Ahmed Abdelsalam (Cisco Systems), Angelo Tulumello (University of Rome Tor Vergata), Marco Bonola (CNIT – National Inter University Consortium for Telecommunications), Stefano Salsano (University of Rome Tor Vergata), Clarence Filsfils (Cisco Systems)
    • 14:30 – 15:00, GMT
      Panel discussion

  • 15:00 – 15:30, GMT

    Coffee break

  • 15:30 – 16:45, GMT

    Session 3: Architectures and Platforms

    • 15:30 – 15:45, GMT
      Compiling Packet Programs to Reconfigurable Switches: Theory and Algorithms. Balázs Vass (Budapest University of Technology and Economics), Erika Bérczi-Kovács (Eötvös Loránd Science University), Costin Raiciu (University Politehnica of Bucharest), Gábor Rétvári (Budapest University of Technology and Economics)
    • 15:45 – 16:00, GMT
      Leveraging Target-specific Features Through P4. Alex Seibulescu (Pensando Systems, Inc.), Mario Baldi (Pensando Systems, Inc.)
    • 16:00 – 16:15, GMT
      MTPSA: Multi-Tenant Programmable Switches. Radostin Stoyanov (University of Cambridge), Noa Zilberman (University of Oxford)
    • 16:15 – 16:45, GMT
      Panel discussion

  • 16:45 – 17:00, GMT

    Closing words

  • 17:00 – 18:00, GMT

    Virtual social event

Important Dates

Abstract registration: Tuesday September 1st, 2020 (11:59PM AoE)
Abstract registration and Paper submission deadline: Tuesday, September 8th, 2020 (11:59PM AoE)
Acceptance notification: Monday, October 5th, 2020
Posters and demos deadline: Tuesday, September 8th, 2020 (11:59PM AoE)
Posters and demos notification: Monday, October 5th, 2020.
Camera ready: Thursday, October 29th, 2020 (11:59PM AoE)
Video upload: Wednesday, November 18th, 2020 (11:59PM AoE)


As a consequence of the current situation of the COVID-19 pandemic and similar to CoNEXT’20, EuroP4’20 will be a fully virtual (online) event. Please follow the updates on the CoNEXT’20 and our website for the details.


Registration is through CoNEXT 2020

General Chairs

Noa Zilberman, University of Cambridge
Robert Soulé, Yale University

Program Chairs

Fernando Ramos, University of Lisbon
Gabor Retvari, Budapest University of Technology and Economics

Technical Program Committee

Aurojit Panda, New York University
Ben Pfaff, VMware
Brian O’Connor, Open Networking Foundation
Christian Rothenberg, University of Campinas
Gianni Antichi, Queen Mary University of London
Gordon Brebner, Xilinx Labs
Jon Crowcroft, University of Cambridge
Marco Chiesa, KTH Royal Institute of Technology
Mario Baldi, Pensando Systems & Politecnico di Torino
Mina Tahmasbi Arashloo, Cornell University
Nate Foster, Cornell University
Paolo Costa, Microsoft Research
Roberto Bifulco, NEC Labs Europe
Sandor Laki, Eötvös Loránd University
Shir Landau Feibish, Princeton University
Theo Jepsen, Stanford University


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